The present invention relates to store buffer forwarding in microprocessors, and more particularly, to multiple store buffer forwarding in a microprocessor system with a restrictive memory model.
Many modern microprocessors implement store buffer forwarding which is a mechanism that improves microprocessor performance by completing a younger dependent load operation by using data from an older, completely overlapping store operation. This forwarding can occur while the store operation is speculative or has passed the point of speculation and is part of the committed machine state. In either case, the load operation""s execution is delayed minimally when it can read its data directly from the buffer without waiting for that data to become globally observed (GO). For multiple store operations, prior processors, such as the Intel(copyright) Pentium(copyright) III, and the related instruction set architectures (ISAs) that run on these processors have stalled the execution of the load operation until the older multiple store operations become globally observed. The Intel(copyright) Pentium(copyright) III is manufactured by Intel Corporation of Santa Clara, Calif.
Because store buffer forwarding has implications on the order in which all processes in a multi-threaded or multi-processor system observe store operations from the other processes, a processor architecture must carefully specify the rules under which store buffer forwarding may occur. For example, the Intel(copyright) Architecture 32-bit ISA (IA-32) product family has essentially implemented the Scalable Processor Architecture (SPARC(copyright)) total store order (TSO) memory model from SPARC International Inc.(trademark) of Santa Clara, Calif.
The TSO memory model has two restrictions related to store buffer forwarding:
1. A younger load operation may only receive forwarded data from a single older store buffer entry; and
2. The older store buffer entry must completely cover the region of memory being read by the younger load operation.
Many existing IA-32 code sequences produce situations in which these two TSO restrictions considerably degrade the performance of the processor. When a typical IA-32 processor executes a load operation that encounters one of the conditions listed above, the processor stalls the load operation""s execution until the offending condition clears. While waiting for the contents of the store buffer entry to become GO, the load operation and all instructions that are dependent on the load operation are stalled, thus reducing processor performance.